The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In one example, an atomic layer deposition process is utilized to from a thin film. The atomic layer deposition technique deposits a thin film with a controlled deposition but has disadvantages of low deposition rate and decreased fabrication throughput. A spatial atomic layer deposition is proposed to deposition a thin film with a controlled deposition and improved deposition rate. However, available spatial atomic deposition has other issues, such as degraded film uniformity and degraded film quality. Accordingly, it would be desirable to provide a spatial atomic layer deposition and a method of utilizing thereof absent the disadvantages discussed above.